Integrated semiconductor devices are typically constructed en masse on a wafer of silicon or gallium arsenide. Each device generally takes the form of an integrated circuit (IC) die, which is attached to a leadframe with gold wires. The die and leadframe are then encapsulated in a plastic or ceramic package, which is then recognizable as an IC (integrated circuit). ICs come in a variety of forms such as dynamic random access memory (DRAM) ICs, static random access memory (SRAM) ICs, read only memory (ROM) ICs, gate arrays, and so forth. The ICs are interconnected in myriad combinations on printed circuit boards by a number of techniques, such as socketing and soldering.
Interconnections among ICs arrayed on printed circuit boards are typically made by conductive traces formed by photolithography and etching processes.
Such semiconductor devices typically take the form of a semiconductor die. The die is generally electrically attached to a leadframe within a package. The leadframe physically supports the die and provides electrical connections between the die and outside world. The die is generally electrically attached to the leadframe by means of fine gold wires. These fine gold wires function to connect the die to the leadframe, so that the gold wires are electrically in series with the leadframe leads. The leadframe and die is then encapsulated, in the form of the familiar integrated circuit. The packaged chip is then able to be installed on a circuit board by any number of techniques, such as socketing and soldering.
The SIMM is a highly space-efficient memory board having no on-board address circuity and which some types of circuit arrays, such as SIMMs (single in line memory module), are designed to plug busses of a computer so that the randomly-addressable memory cells of the SIMM can be addressed directly by the computer's CPU rather than by a bank-switching technique commonly used in larger memory expansion boards. Memory cells on the SIMM are perceived by the computer's CPU as being no different than memory cells found on the computer's mother board. Since SIMMs are typically populated with byte multiple of DRAMs, for any eight bit byte of sixteen bit byte or word of information stored within a SIMM, each of the component bits will be found on a separate chip and will be individually addressable by column and row. One edge of a SIMM module is a card-edge connector, which plugs into a socket on the computer which is directly connected to the computer busses required for powering and addressing the memory on the SIMM.
These modules have been constructed by first packaging individual dice (IC chips) into packages, and then soldering the packaged chips onto a printed circuit board. The chips had been attached by surface mount techniques (e.g. PLCC chips) or into through holes (e.g. DIP packaged chips). While this facilitates discrete testing prior to module assembly, no advantage is taken of the module (SIMM) level assembly in connecting the dice to their leadframes.
Other circuits which are constructed from standard components have in the past used discretely encapsulated integrated circuits (Ics) which are then fixed to a printed circuit board. Large scale integrated (LSI) circuits had been used to reduce or eliminate multiplicity of encapsulation operations, but LSI techniques require that each mask step required for each part of the circuit be performed on a wafer used to form the entire circuit.
On circuits with low yields, it is often desirable to fabricate the circuit in segments, and then assemble the completed segments at a board level. Thus, DRAMs are fabricated in excess of 100 dice per wafer, and the dice are separated, even though the computer may have a high number of DRAMs installed as RAM memory. This is done because individual chips will vary in performance across a wafer and because yield tends to diminish as attempts are made to expand memory size. By individually packaging chips and then assembling arrays of chips at a board level, parts may be segregated according to performance and the use of failed parts may be avoided.
When increasing the circuitry on a single integrated circuit, care must be taken to ascertain that the processes which are used to fabricate each circuit element are compatible. Even in cases where, for example, state of the art DRAM technology is used in design of logic chips, the optimum process parameters for different types of circuits will vary. As an example, it is difficult to provide a single chip with both a microprocessor and a memory array.
Thus, a VLSI chip has the advantage of packaging a large number of circuits onto a single leadframe, but requires that a variety of circuits share the same process steps. It would be desirable to provide multiple circuits which are grouped after fabrication into a single integrated circuit package. It would also be desirable to provide circuits which are manufactured under different process steps as a single integrated circuit package.
Interconnects consist of unsupported sections of Cu traces on a plurality of planes. The circuits on each plane are positioned so that the appropriate Cu traces are aligned over and under each other. The unsupported traces will meet each other between the upper and lower planes. All Cu to Cu interconnects can be formed simultaneously. The spacing between the circuit planes will be optimized for thermal, mechanical, and electrical properties. It is anticipated that the smaller geometries common with TAB circuitry will provide a significant improvement in electrical properties so that the conventional power and ground plane layers can be eliminated.
The polymer/Cu circuit now "loaded" with ICs is electrically functional and ready for functional testing, but still lacks physical package support.
In alternate embodiments, a TAB circuit with ICs mounted to the TAB circuit is encapsulated on one or both sides, with external terminations exposed for subsequent connections.
The techniques used for assembling arrays of similar circuits are also applicable for forming circuit modules of unlike circuits. In such an arrangement, the individual dice are mounted to the TAB printed wire assembly (PWA) and the dice are encapsulated subsequent to the dice being mounted. While this technique can be used for most board level products, it is particularly suitable for products in which it would be uneconomical to replace components on the board instead of replacing the entire board. External connections are provided either as a part of the encapsulated TAB PWA, or by attaching an appropriate connector to the PWA.
This enables an encapsulated assembly to be formed in circumstances where an LSI circuit would be ideal for assembly purposes, but the yields of manufacturing LSI circuits would result in undue expense.
It is proposed that multiple integrated circuit devices be packaged as a single unit, known as a multi chip module (MCM). This can be accomplished with or without conventional lead frames. This creates two problems compared to conventional test methods. Firstly, discrete testing is more difficult because the conventional lead frame package is not used. Furthermore, when multiple devices are assembled into a single package, the performance of the package is reduced to that of the die with the lowest performance. In other words, the ability to presort the individual dice is limited to that obtained through probe testing. Secondly, the packaging may have other limitations which are aggravated by burn-in stress conditions so that the packaging becomes a limitation for burn-in testing.
MCMs create a particular need for testing prior to assembly, as contrasted to the economics of testing parts which are discretely packaged as singulated parts. For discretely packaged parts, if the product yield of good parts from preliminary testing to final shipment (probe-to-ship) is, for example, 95%, one would not be particularly concerned with packaging costs for the failed parts, if packaging costs are 10% of the product manufacturing costs. Even where packaging costs are considerably higher, as in ceramic encapsulated parts, testing unpackaged die is economical for discretely packaged parts when the added costs approximates that of cost of packaging divided by yield: EQU C.sub.DIE .times.C.sub.PACKAGE /YIELD=C.sub.DIE .times.C
where
C=cost PA1 C.sub.DIE =manufacturing cost of functional die PA1 C.sub.ADDL.KGD =additional cost of testing unpackaged die in order to produce known good die (KGD)
Note that in the case of discretely packaged parts, the cost of the die (C.sub.DIE) is essentially not a factor. This changes in the case of MCMs: ##EQU1## Note that again C.sub.DIE is not a factor in modules having identical part types; however, the equation must be modified to account for varied costs and yields of die in modules with mixed part types. With MCMs, the cost of packaging a failed part is proportional to the number of die in the module. In the case of a x16 memory array module, where probe-to-ship yield of the die is 95%, the costs are: ##EQU2## so the additional costs of testing for known good die (KGD) may be 16 times the cost of testing after assembly of an unrepairable module in order to be economical. This, of course, is modified by the ability to repair failed modules.
More complex systems, involving more semiconductor die, present more opportunity for failure. Therefore, it is advantageous that modules be configured so the module be able to be tested in component parts which may be assembled after testing.
Conventional computer systems, whether general purpose, desktop, work stations, or imbedded controllers (e.g., small computers used to control tools, instruments, or appliances), all include some form of read/write memory. At the present time, the most popular form of read/write memory is the semiconductor DRAM (or Dynamic Random Access Memory).
The maximum operating speed of a computer device depends on two things: how fast the processor can execute instructions, and how long it has to wait for instructions or data. As speeds increase, the capability of connecting circuity becomes a limiting factor. Thus, a microprocessor may operate at speeds which exceed the capabilities of the circuit board to which the microprocessor is intended to be mounted.
One solution to the problem of speed limitations of circuit boards is a "speed doubler" or "speed multiplier" circuit. The speed multiplier circuit permits a circuit to operate at a higher clock speed than its associated system components. In one example, a microprocessor is operated with a speed multiplier, while a motherboard to which the microprocessor is mounted operates at a lower clock speed. In such speed multiplier circuits, the high speed operations are limited to the component with the speed multiplier. Operations which are external to that component remain speed limited.
Multichip modules have the advantage that they avoid some of the speed limitations of the circuit board (motherboard). MCMs also have the disadvantage of requiring that a large number of semiconductor die be tested and matched prior to assembly. It would be advantageous if multiple MCMs could be assembled without signals being required to pass through a separate circuit board. This would in effect result in the assembly of a larger MCM.
Often it is desired to increase the capabilities and performance of a computer by adding components. If such components are to be made a part of a multichip module, the change would require a reconfiguration of the module. It would be desirable to permit a computer or other electronic device to be constructed with a multichip module architecture, but still permit reconfiguration of the architecture after the electronic device is assembled.
Integrated circuit technology provides performance capabilities beyond conventional PCB board and packaging technologies. Multichip modules represent a solution to allow integrated circuit performance to be fully realized at the module level. MCM development is severely limited by the high costs associated with design and simulation, component yield, and rework.